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» On the Circuit Implementation Problem
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DSD
2010
IEEE
171views Hardware» more  DSD 2010»
15 years 5 months ago
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
Jiri Balcarek, Petr Fiser, Jan Schmidt
JMLR
2010
111views more  JMLR 2010»
15 years 1 months ago
An EM Algorithm on BDDs with Order Encoding for Logic-based Probabilistic Models
Logic-based probabilistic models (LBPMs) enable us to handle problems with uncertainty succinctly thanks to the expressive power of logic. However, most of LBPMs have restrictions...
Masakazu Ishihata, Yoshitaka Kameya, Taisuke Sato,...
TCAD
2010
112views more  TCAD 2010»
15 years 1 months ago
Multilayer Global Routing With Via and Wire Capacity Considerations
Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a sim...
Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
TE
2010
168views more  TE 2010»
15 years 1 months ago
Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education
The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test educat...
John Hu, Mark Haffner, Samantha Yoder, Mark Scott,...
ETS
2011
IEEE
230views Hardware» more  ETS 2011»
14 years 6 months ago
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak,...