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» On the Circuit Implementation Problem
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DAC
2001
ACM
16 years 8 months ago
Future Performance Challenges in Nanometer Design
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
Dennis Sylvester, Himanshu Kaul
VLSID
2004
IEEE
111views VLSI» more  VLSID 2004»
16 years 7 months ago
On Buffering Schemes for Long Multi-Layer Nets
We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution...
Vani Prasad, Madhav P. Desai
ICCD
2006
IEEE
84views Hardware» more  ICCD 2006»
16 years 4 months ago
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Y...
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
16 years 4 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
16 years 4 months ago
Optimizing yield in global routing
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
Dirk Müller