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» On the Circuit Implementation Problem
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VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 7 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
16 years 4 months ago
Scalable and scalably-verifiable sequential synthesis
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
Alan Mishchenko, Michael L. Case, Robert K. Brayto...
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
16 years 4 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
16 years 1 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
ICCCN
2007
IEEE
16 years 1 months ago
Low-Latency Multichannel Wireless Mesh Networks
—Multimedia requirements of the 1990’s drove wired and optical network architects to reconsider the inefficiencies of packet switching and consider long proven methods such as...
Robert McTasney, Dirk Grunwald, Douglas C. Sicker