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» On the Circuit Implementation Problem
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ISLPED
1997
ACM
96views Hardware» more  ISLPED 1997»
15 years 11 months ago
Re-mapping for low power under tight timing constraints
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
HICSS
1996
IEEE
102views Biometrics» more  HICSS 1996»
15 years 11 months ago
Evaluation of Parallel Logic Simulation Using DVSIM
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulati...
Gerd Meister
DAC
1996
ACM
15 years 11 months ago
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction
In this paper, we describe how we have improved the efficiency of a finite-element method for interconnect resistance extraction by introducingarticulation nodes in the finiteelem...
Arjan J. van Genderen, N. P. van der Meijs
BROADNETS
2007
IEEE
15 years 11 months ago
Generic optical network provisioning services to support emerging grid applications
Emerging high-end applications require a rich set of network provisioning services that go beyond the traditional source-destination, end-to-end path service. They also require hig...
Yufeng Xin, Lina Battestilli, Gigi Karmous-Edwards
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
15 years 10 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...