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» On the Circuit Implementation Problem
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FPL
2005
Springer
100views Hardware» more  FPL 2005»
16 years 17 days ago
HAIL: A Hardware-Accelerated Algorithm for Language Identification
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
FPL
2005
Springer
115views Hardware» more  FPL 2005»
16 years 17 days ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
16 years 9 days ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
ISCAS
2003
IEEE
117views Hardware» more  ISCAS 2003»
16 years 9 days ago
Learning temporal correlations in biologically-inspired aVLSI
Temporally-asymmetric Hebbian learning is a class of algorithms motivated by data from recent neurophysiology experiments. While traditional Hebbian learning rules use mean firin...
Adria Bofill-i-Petit, Alan F. Murray
ITC
2003
IEEE
172views Hardware» more  ITC 2003»
16 years 9 days ago
First IC Validation of IEEE Std. 1149.6
–This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST_PULSE tests...
Suzette Vandivier, Mark Wahl, Jeff Rearick