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DATE
2005
IEEE
107views Hardware» more  DATE 2005»
16 years 19 days ago
On Statistical Timing Analysis with Inter- and Intra-Die Variations
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
Hratch Mangassarian, Mohab Anis
ICRA
2005
IEEE
155views Robotics» more  ICRA 2005»
16 years 19 days ago
CPG Design using Inhibitory Networks
– We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordina...
M. Anthony Lewis, Francesco Tenore, Ralph Etienne-...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
16 years 18 days ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ISCAS
2005
IEEE
143views Hardware» more  ISCAS 2005»
16 years 18 days ago
Biasing techniques for subthreshold MOS resistive grids
— A classic resistive network implemented using MOS transistors suffers from non-linearity in the subthreshold exponential parameter κ that arises due to varying VGB and VBS. We...
Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar
EDCC
2005
Springer
16 years 17 days ago
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSB...
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jut...