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» On the Circuit Implementation Problem
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ASPDAC
2004
ACM
87views Hardware» more  ASPDAC 2004»
16 years 13 days ago
ShatterPB: symmetry-breaking for pseudo-Boolean formulas
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
16 years 13 days ago
Multilevel routing with antenna avoidance
As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide...
Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
ISCAS
2003
IEEE
119views Hardware» more  ISCAS 2003»
16 years 9 days ago
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning
In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective versio...
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
ISCAS
2003
IEEE
90views Hardware» more  ISCAS 2003»
16 years 9 days ago
A reduction technique of large scale RCG interconnects in complex frequency domain
High frequency digital LSIs usually consist of many subcircuits coupled with multi-conductor interconnects embedded in the substrate. They sometimes cause serious problems of the ...
Yoshihiro Yamagami, Yoshifumi Nishio, Atsumi Hatto...
DAC
2000
ACM
15 years 11 months ago
Block placement with symmetry constraints based on the O-tree non-slicing representation
The ordered tree (O-tree) representation has recently gained much interest in layout design automation. Different from previous topological representations of non-slicing floorpl...
Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-...