As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...