10718 search results - page 461 / 2144 » On the Circuit Implementation Problem |
191
click to vote
GLVLSI
2000
IEEE
15 years 11 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
179
Voted
ITC
1999
IEEE
15 years 11 months ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...
155
click to vote
MFCS
1998
Springer
15 years 11 months ago
1998
Springer
In this paper we consider the problem of characterizing optimal variable orderings for shared OBDDs of two Boolean functions fi = gi i hi, i = 1, 2, where i is an operator from th...
206
click to vote
ITC
1993
IEEE
15 years 11 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
199
click to vote
DAC
2010
ACM
15 years 11 months ago
2010
ACM
The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we...