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» On the Circuit Implementation Problem
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ARITH
2009
IEEE
16 years 1 months ago
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
Ghassem Jaberipur, Behrooz Parhami
ISLPED
2006
ACM
122views Hardware» more  ISLPED 2006»
16 years 28 days ago
Dynamic thermal clock skew compensation using tunable delay buffers
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
16 years 15 days ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong
DATE
2003
IEEE
152views Hardware» more  DATE 2003»
16 years 8 days ago
Synthesis of CMOS Analog Cells Using AMIGO
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud...
COCO
2003
Springer
145views Algorithms» more  COCO 2003»
16 years 6 days ago
Hardness vs. Randomness within Alternating Time
We study the complexity of building pseudorandom generators (PRGs) with logarithmic seed length from hard functions. We show that, starting from a function f : {0, 1}l → {0, 1} ...
Emanuele Viola