10718 search results - page 444 / 2144 » On the Circuit Implementation Problem |
148
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GLVLSI
2010
IEEE
16 years 1 days ago
2010
IEEE
This paper investigates read-out schemes for a crossbar memory using CNTFET-based elements as cross-points. Two read-out schemes are presented in this paper; the first scheme bias...
143
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DFT
2002
IEEE
15 years 12 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
163
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
151
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
200
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...