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» On the Circuit Implementation Problem
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GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
16 years 1 months ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
ISCAS
2005
IEEE
104views Hardware» more  ISCAS 2005»
16 years 16 days ago
On the three-dimensional channel routing
— The 3-D channel routing is a fundamental problem on the physical design of 3-D integrated circuits. The 3-D channel is a 3-D grid G and the terminals are vertices of G located ...
Satoshi Tayu, Patrik Hurtig, Yoshiyasu Horikawa, S...
HICSS
2003
IEEE
119views Biometrics» more  HICSS 2003»
16 years 7 days ago
A First Person IP over HDSL Case Study
As many authors have articulated, the “last mile problem” is often cited as a persistent engineering obstacle in deploying residential broadband solutions. Additionally, some ...
Wayne Smith
ISPD
2003
ACM
92views Hardware» more  ISPD 2003»
16 years 5 days ago
Benchmarking for large-scale placement and beyond
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved i...
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov...
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
16 years 1 days ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi