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» On the Circuit Implementation Problem
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CHES
2005
Springer
100views Cryptology» more  CHES 2005»
16 years 14 days ago
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on imple...
Thomas Popp, Stefan Mangard
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
16 years 6 days ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
ITC
2003
IEEE
115views Hardware» more  ITC 2003»
16 years 6 days ago
Towards Structural Testing of Superconductor Electronics
Many of the semiconductor technologies are already facing limitations while new-generation data and telecommunication systems are implemented. Although in its infancy, superconduc...
Arun A. Joseph, Hans G. Kerkhoff
ICCAD
2002
IEEE
160views Hardware» more  ICCAD 2002»
15 years 12 months ago
Folding of logic functions and its application to look up table compaction
The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic func...
Shinji Kimura, Takashi Horiyama, Masaki Nakanishi,...
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
15 years 11 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft