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DATE
2002
IEEE
158views Hardware» more  DATE 2002»
15 years 12 months ago
Congestion Estimation with Buffer Planning in Floorplan Design
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Yo...
ISCAS
2002
IEEE
118views Hardware» more  ISCAS 2002»
15 years 12 months ago
A curvature compensation technique for bandgap voltage references using adaptive reference temperature
– A curvature compensation technique for bandgap voltage references that utilizes an adaptive reference temperature is presented. This compensation technique is intended for high...
Kee-Chee Tiew, J. Cusey, Randall L. Geiger
ITC
1999
IEEE
59views Hardware» more  ITC 1999»
15 years 11 months ago
Static component interconnection test technology in practice
Static Component Interconnection Test Technology (SCITT) is a new XNOR circuit based technology that is used for board-level interconnection test. SCITT provides an easy test meth...
Frans De Jong, Rob Raaijmakers
RSP
1998
IEEE
109views Control Systems» more  RSP 1998»
15 years 10 months ago
A Technique for Combined Virtual Prototyping and Hardware Design
A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the ...
Patrick Schaumont, Geert Vanmeerbeeck, E. Watzeels...
ISLPED
1995
ACM
113views Hardware» more  ISLPED 1995»
15 years 10 months ago
Low delay-power product CMOS design using one-hot residue coding
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
William A. Chren Jr.