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ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
16 years 3 months ago
Timing optimization by restructuring long combinatorial paths
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
Jürgen Werber, Dieter Rautenbach, Christian S...
ICCAD
2002
IEEE
110views Hardware» more  ICCAD 2002»
16 years 3 months ago
Whirlpool PLAs: a regular logic structure and their synthesis
 A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
Fan Mo, Robert K. Brayton
DSD
2008
IEEE
125views Hardware» more  DSD 2008»
16 years 1 months ago
On the Complexity of Error Detection Functions for Redundant Residue Number Systems
This paper considers a single-digit error detection in a Redundant Residue Number System (RRNS). Let f be the function that denotes the set of legitimate codes of an RRNS. To anal...
Tsutomu Sasao, Yukihiro Iguchi
ISMVL
2008
IEEE
134views Hardware» more  ISMVL 2008»
16 years 1 months ago
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells
Nanoscale multiple-valued logic systems require the development of nanometer scale integrated circuits and components. Due to limits in device physics, new components must be deve...
Theodore W. Manikas, Dale Teeters
DFT
2007
IEEE
109views VLSI» more  DFT 2007»
16 years 1 months ago
Safety Evaluation of NanoFabrics
Chemically Assembled Electronic Nanotechnology is a promising alternative to CMOS fabrication. In particular, the nanoFabric has proven to be a viable solution for implementing di...
Michelangelo Grosso, Maurizio Rebaudengo, Matteo S...