10718 search results - page 386 / 2144 » On the Circuit Implementation Problem |
181
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
175
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
We present an efficient implementation of an approximate balanced truncation model reduction technique for general large-scale RLC systems, described by a statespace model where t...
228
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ICCD
2008
IEEE
16 years 3 months ago
2008
IEEE
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
175
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
173
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FPGA
2010
ACM
16 years 3 months ago
2010
ACM
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...