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» On the Circuit Implementation Problem
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FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
15 years 8 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong
JCP
2008
141views more  JCP 2008»
15 years 6 months ago
Leakage Controlled Read Stable Static Random Access Memories
Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a criti...
Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Law...
CG
2005
Springer
15 years 6 months ago
Combining geometry and domain knowledge to interpret hand-drawn diagrams
One main challenge in building interpreters for hand-drawn sketches is the task of parsing a sketch to locate the individual symbols. Many existing pen-based systems avoid this pr...
Leslie Gennari, Levent Burak Kara, Thomas F. Staho...
TCAD
1998
115views more  TCAD 1998»
15 years 6 months ago
Probabilistic modeling of dependencies during switching activity analysis
—This paper addresses, from a probabilistic point of view, the issue of switching activity estimation in combinational circuits under the zero-delay model. As the main theoretica...
Radu Marculescu, Diana Marculescu, Massoud Pedram
GLOBECOM
2010
IEEE
15 years 4 months ago
Energy-Efficient Power Loading for a MIMO-SVD System and Its Performance in Flat Fading
In this paper we formulate a power loading problem for the spatial subchannels (parallel channels) of a single-carrier MIMO-SVD system. The power loading solution is designed to mi...
Raghavendra S. Prabhu, Babak Daneshrad