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» On the Circuit Implementation Problem
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DATE
2005
IEEE
118views Hardware» more  DATE 2005»
16 years 14 days ago
A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems
—Presented are a methodology and a DFII-based tool for AC-stability analysis of a wide variety of closed-loop continuous-time (operational amplifiers and other linear circuits). ...
Momchil Milev, Rod Burt
APN
2005
Springer
16 years 11 days ago
Determinate STG Decomposition of Marked Graphs
STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondet...
Mark Schäfer, Walter Vogler, Petr Jancar
CHARME
2005
Springer
136views Hardware» more  CHARME 2005»
16 years 11 days ago
Acceleration of SAT-Based Iterative Property Checking
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
Daniel Große, Rolf Drechsler
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
16 years 4 days ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
EH
2003
IEEE
117views Hardware» more  EH 2003»
16 years 4 days ago
The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
Robert Thomson, Tughrul Arslan