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DATE
2010
IEEE
109views Hardware» more  DATE 2010»
15 years 12 months ago
TIMBER: Time borrowing and error relaying for online timing error resilience
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram...
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
15 years 11 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
DAC
1994
ACM
15 years 10 months ago
Acyclic Multi-Way Partitioning of Boolean Networks
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
Jason Cong, Zheng Li, Rajive Bagrodia
AICT
2006
IEEE
135views Communications» more  AICT 2006»
15 years 10 months ago
Improving Web Performance through New Networking Technologies
New connection-oriented networking technologies can provide quality-of-service guaranteed network connectivity required by some web-based applications. In this paper, we present a...
Xiuduan Fang, Xuan Zheng, Malathi Veeraraghavan
DATE
2004
IEEE
210views Hardware» more  DATE 2004»
15 years 10 months ago
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...