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» On the Circuit Implementation Problem
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IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
16 years 23 days ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
ASPDAC
2006
ACM
110views Hardware» more  ASPDAC 2006»
16 years 21 days ago
Switching-activity driven gate sizing and Vth assignment for low power design
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
ICCD
2000
IEEE
120views Hardware» more  ICCD 2000»
15 years 11 months ago
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Viresh Paruthi, Andreas Kuehlmann
FSTTCS
2006
Springer
15 years 10 months ago
Some Results on Average-Case Hardness Within the Polynomial Hierarchy
Abstract. We prove several results about the average-case complexity of problems in the Polynomial Hierarchy (PH). We give a connection among average-case, worst-case, and non-unif...
Aduri Pavan, Rahul Santhanam, N. V. Vinodchandran
ICCAD
1995
IEEE
110views Hardware» more  ICCAD 1995»
15 years 10 months ago
Fast functional simulation using branching programs
This paper addresses the problem of speeding up functional (delayindependent)logic simulation for synchronousdigital systems. The problem needs very little new motivation – cycl...
Pranav Ashar, Sharad Malik