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ESANN
2004
15 years 8 months ago
Neural Hardware: beyond ones and zeros
An overview of research on the implementation of neural systems is presented in this paper. We focus on implementations where the algorithms and their physical support are tightly ...
Patrice Fleury, Adria Bofill-i-Petit, Alan F. Murr...
NIPS
1996
15 years 8 months ago
A Micropower Analog VLSI HMM State Decoder for Wordspotting
We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decod...
John Lazzaro, John Wawrzynek, Richard Lippmann
MEMOCODE
2010
IEEE
15 years 4 months ago
FPGA-based combined architecture for stream categorization and intrusion detection
This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The s...
Sunil Shukla, Rodric Rabbah, Martin Vorbach
ICMCS
2006
IEEE
154views Multimedia» more  ICMCS 2006»
16 years 22 days ago
Implementation and Evolution of Packet Striping for Media Streaming Over Multiple Burst-Loss Channels
Modern mobile devices are multi-homed with WLAN and WWAN communication interfaces. In a community of nodes with such multihomed devices — locally inter-connected via high-speed ...
Gene Cheung, Puneet Sharma, Sung-Ju Lee
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
15 years 12 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...