A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
This paper presents mathematical foundtions of the Overlap Resolution Number System (ORNS) which employs signed Continuous Valued Digits (CVD's). ORNS is a redundant Number S...
This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to mul...
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vran...
We describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic ...
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
Jo C. Ebergen, Daniel Finchelstein, Russell Kao, J...