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» On the Circuit Implementation Problem
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EUROGP
2000
Springer
116views Optimization» more  EUROGP 2000»
15 years 10 months ago
An Extrinsic Function-Level Evolvable Hardware Approach
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
Tatiana Kalganova
DAC
1989
ACM
15 years 10 months ago
An Efficient Finite Element Method for Submicron IC Capacitance Extraction
We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the cond...
N. P. van der Meijs, Arjan J. van Genderen
CC
2008
Springer
240views System Software» more  CC 2008»
15 years 8 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
FPL
2008
Springer
180views Hardware» more  FPL 2008»
15 years 8 months ago
Compiled hardware acceleration of Molecular Dynamics code
The objective of Molecular Dynamics (MD) simulations is to determine the shape of a molecule in a given biomolecular environment. These simulations are very demanding computationa...
Jason R. Villarreal, Walid A. Najjar
FPL
2008
Springer
124views Hardware» more  FPL 2008»
15 years 8 months ago
Direct sigma-delta modulated signal processing in FPGA
The effectiveness of implementing bit-stream signal processing (BSSP) multiplier circuits in FPGAs, in terms of hardware resources and clock frequency, is presented. In particular...
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-S...