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ISMVL
2010
IEEE
158views Hardware» more  ISMVL 2010»
15 years 10 months ago
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
—Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several clas...
Alexander Finder, Rolf Drechsler
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
AAAI
1994
15 years 8 months ago
Noise Strategies for Improving Local Search
It has recently been shown that local search is surprisingly good at nding satisfying assignments for certain computationally hard classes of CNF formulas. The performance of basi...
Bart Selman, Henry A. Kautz, Bram Cohen
KES
2008
Springer
15 years 6 months ago
Incremental evolution of a signal classification hardware architecture for prosthetic hand control
Evolvable Hardware (EHW) is a new method for designing electronic circuits. However, there are several problems to solve for making high performance systems. One is the limited sca...
Jim Torresen
ATS
2010
IEEE
253views Hardware» more  ATS 2010»
15 years 4 months ago
On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and o...
Xiao Liu, Qiang Xu