We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically ...
Brent Goplen, Prashant Saxena, Sachin S. Sapatneka...
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
In general, automatic layout composition techniques based on pre-designed devices facilitate the production of small IC numbers by prefabricating their basic structures. They also...