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» On the Circuit Implementation Problem
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DAC
2005
ACM
16 years 7 months ago
Net weighting to reduce repeater counts during placement
We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically ...
Brent Goplen, Prashant Saxena, Sachin S. Sapatneka...
ICCD
2003
IEEE
109views Hardware» more  ICCD 2003»
16 years 3 months ago
Independent Test Sequence Compaction through Integer Programming
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
Petros Drineas, Yiorgos Makris
VTS
2002
IEEE
101views Hardware» more  VTS 2002»
15 years 11 months ago
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
Shi-Yu Huang
EVOW
1999
Springer
15 years 11 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
ICCD
1996
IEEE
108views Hardware» more  ICCD 1996»
15 years 10 months ago
Module Generators for a Regular Analog Layout
In general, automatic layout composition techniques based on pre-designed devices facilitate the production of small IC numbers by prefabricating their basic structures. They also...
J. Kampe, C. Wisser, G. Scarbata