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FPGA
2004
ACM
117views FPGA» more  FPGA 2004»
15 years 11 months ago
A magnetoelectronic macrocell employing reconfigurable threshold logic
In this paper, we introduce a reconfigurable fabric based around a new class of circuit element: the hybrid Hall effect (HHE) magnetoelectronic device. Because they incorporate a ...
Steve Ferrera, Nicholas P. Carter
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 10 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
IOLTS
2008
IEEE
91views Hardware» more  IOLTS 2008»
16 years 23 days ago
Physical Demonstration of Polymorphic Self-Checking Circuits
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose ...
Richard Ruzicka, Lukás Sekanina, Roman Prok...
DDECS
2007
IEEE
121views Hardware» more  DDECS 2007»
16 years 21 days ago
A Novel Parity Bit Scheme for SBox in AES Circuits
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouze...
IWSOC
2005
IEEE
141views Hardware» more  IWSOC 2005»
15 years 12 months ago
Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
Kenneth A. Townsend, James W. Haslett, Krzysztof I...