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ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
15 years 10 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
CVRMED
1997
Springer
15 years 10 months ago
An approach to 2D/3D registration of a vertebra in 2D X-ray fluoroscopies with 3D CT images
In order to use pre-operative images during an operation for navigation, they must be registered to the patient's coordinate system in the operating theater or to an intra-ope...
Jürgen Weese, Thorsten M. Buzug, Cristian Lor...
CAV
2010
Springer
187views Hardware» more  CAV 2010»
15 years 10 months ago
Fences in Weak Memory Models
We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and the visibility of inter- and intra-pr...
Jade Alglave, Luc Maranget, Susmit Sarkar, Peter S...
WCNC
2010
IEEE
15 years 10 months ago
A Lightweight Distributed Solution to Content Replication in Mobile Networks
Abstract—Performance and reliability of content access in mobile networks is conditioned jointly by the number and location of content replicas deployed at the network nodes. The...
C.-A. La, Pietro Michiardi, Claudio Casetti, Carla...
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
15 years 10 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...