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ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
15 years 11 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
DAC
2002
ACM
16 years 7 months ago
A flexible accelerator for layer 7 networking applications
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
Gokhan Memik, William H. Mangione-Smith
DELTA
2006
IEEE
15 years 9 months ago
Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmabl
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
Peter J. Green, Desmond P. Taylor
HPCS
2007
IEEE
16 years 14 days ago
Improved Grid Metascheduler Design using the Plackett-Burman Methodology
In the context of computational grids, a metascheduler is the service responsible for scheduling jobs across many geographically distributed processor clusters. Typically, these s...
Daniel C. Vanderster, Nikitas J. Dimopoulos, Randa...
DAC
1998
ACM
16 years 7 months ago
Design and Implementation of the NUMAchine Multiprocessor
This paper describes the design and implementation of the NUMAchine multiprocessor. As the market for CC-NUMA multiprocessors expands, this research project provides a timely arch...
A. Grbic, Stephen Dean Brown, S. Caranci, R. Grind...