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» On software design for stochastic processors
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DAC
1999
ACM
16 years 7 months ago
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, H...
HIPEAC
2010
Springer
16 years 3 months ago
Scalable Shared-Cache Management by Containing Thrashing Workloads
Abstract. Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the m...
Yuejian Xie, Gabriel H. Loh
AES
2000
Springer
98views Cryptology» more  AES 2000»
15 years 10 months ago
How Well Are High-End DSPs Suited for the AES Algorithms? AES Algorithms on the TMS320C6x DSP
The National Institute of Standards and Technology (NIST) has announced that one of the design criteria for the Advanced Encryption Standard (AES) algorithm was the ability to e...
Thomas J. Wollinger, Min Wang, Jorge Guajardo, Chr...
ASPDAC
1995
ACM
104views Hardware» more  ASPDAC 1995»
15 years 9 months ago
Power analysis of a 32-bit embedded microcontroller
A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...
Vivek Tiwari, Mike Tien-Chien Lee
HIPEAC
2005
Springer
15 years 11 months ago
Memory-Centric Security Architecture
Abstract. This paper presents a new security architecture for protecting software confidentiality and integrity. Different from the previous process-centric systems designed for ...
Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee