964 search results - page 104 / 193 » On software design for stochastic processors |
226
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LCPC
2009
Springer
15 years 10 months ago
2009
Springer
Programming heterogeneous parallel computer systems is notoriously difficult, but MIMD models have proven to be portable across multi-core processors, clusters, and massively paral...
171
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ARCS
2006
Springer
15 years 10 months ago
2006
Springer
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
148
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CODES
2001
IEEE
15 years 9 months ago
2001
IEEE
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...
160
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CODES
2005
IEEE
15 years 8 months ago
2005
IEEE
Memory bandwidth issues present a formidable bottleneck to accelerating embedded applications, particularly data bandwidth for multiple-issue VLIW processors. Providing an efficie...
176
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ASPLOS
2011
ACM
14 years 9 months ago
2011
ACM
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...