6592 search results - page 152 / 1319 » On robust cycle bases |
153
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IROS
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract— This paper deals with a discret-time control approach, proposed for the control of a five-link, four-actuator planar biped walker. The approach is based on the choice ...
140
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FCCM
2008
IEEE
16 years 1 months ago
2008
IEEE
We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx’s Virtex-5 FPGAs. An iterative “basic” module outputs a 32 bit col...
146
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper presents a new fast and templatized family of fine-grain asynchronous pipeline stages based on the single-track protocol. No explicit control wires are required outside...
166
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ISCA
1999
IEEE
15 years 11 months ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
166
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ASPDAC
2001
ACM
15 years 10 months ago
2001
ACM
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical...