This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mech...
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
This paper describes how the curriculum and course format at the Air Force Institute of Technology (AFIT) has evolved based on our experience with the highly-successful Cyber Defe...
Barry E. Mullins, Timothy H. Lacey, Robert F. Mill...
— This paper demonstrates how two different sets of powerful domain specific language features can be specified and deployed as composable language extensions. These extensions...