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DATE
2007
IEEE
145views Hardware» more  DATE 2007»
16 years 1 months ago
Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
Riccardo Mariani, Gabriele Boschi, Federico Colucc...
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
16 years 1 months ago
A non-intrusive isolation approach for soft cores
Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mech...
Ozgur Sinanoglu, Tsvetomir Petrov
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
HICSS
2007
IEEE
100views Biometrics» more  HICSS 2007»
16 years 1 months ago
The Impact of the NSA Cyber Defense Exercise on the Curriculum at the Air Force Institute of Technology
This paper describes how the curriculum and course format at the Air Force Institute of Technology (AFIT) has evolved based on our experience with the highly-successful Cyber Defe...
Barry E. Mullins, Timothy H. Lacey, Robert F. Mill...
HICSS
2007
IEEE
135views Biometrics» more  HICSS 2007»
16 years 1 months ago
Composable Language Extensions for Computational Geometry: A Case Study
— This paper demonstrates how two different sets of powerful domain specific language features can be specified and deployed as composable language extensions. These extensions...
Eric Van Wyk, Eric Johnson
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