315 search results - page 25 / 63 » On reducing load store latencies of cache accesses |
150
Voted
ASPLOS
1991
ACM
15 years 9 months ago
1991
ACM
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
194
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ICS
2010
Tsinghua U.
15 years 8 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
169
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ICCS
2003
Springer
15 years 11 months ago
2003
Springer
Memory traces record the addresses touched by a program during its execution, enabling many useful investigations for understanding and predicting program performance. But complete...
118
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DATE
2009
IEEE
16 years 25 days ago
2009
IEEE
D-NUCA L2 caches are able to tolerate the increasing wire delay effects due to technology scaling thanks to their banked organization, broadcast line search and data promotion/dem...
190
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ACMMSP
2006
ACM
16 years 2 days ago
2006
ACM
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...