We empirically assess the implications of fixed terminals for hypergraph partitioning heuristics. Our experimental testbed incorporates a leading-edge multilevel hypergraph partit...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
For statistical timing and power analysis that are very important problems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctua...
Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhar...
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...