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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
15 years 6 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
EOR
2006
199views more  EOR 2006»
15 years 6 months ago
Short-term booking of air cargo space
This paper proposes a stochastic dynamic programming model for a short-term capacity planning model for air cargo space. The long-term cargo space is usually acquired by freight fo...
Ek Peng Chew, Huei Chuen Huang, Ellis L. Johnson, ...
SIAMIS
2011
15 years 1 months ago
Large Scale Bayesian Inference and Experimental Design for Sparse Linear Models
Abstract. Many problems of low-level computer vision and image processing, such as denoising, deconvolution, tomographic reconstruction or superresolution, can be addressed by maxi...
Matthias W. Seeger, Hannes Nickisch
LCTRTS
2007
Springer
16 years 19 days ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
AWIC
2003
Springer
15 years 11 months ago
Secure Intelligent Agents Based on Formal Description Techniques
This paper describes a practical solution for the incorporation of security services in agents. From a set of basic user requirements, the agents will be able to find out the best ...
L. Mengual, C. de la Puente