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ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
13 years 9 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
ACMMSP
2006
ACM
260views Hardware» more  ACMMSP 2006»
16 years 13 days ago
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by • time, • TLB misses, • L1 misses, • L2 m...
Michael D. Adams, David S. Wise
TC
1998
15 years 6 months ago
Algorithms for Variable Length Subnet Address Assignment
In a computer network that consists of M subnetworks, the L-bit address of a machine consists of two parts: A pre x si that contains the address of the subnetwork to which the mac...
Mikhail J. Atallah, Douglas Comer
CISS
2007
IEEE
15 years 10 months ago
How Many Users should be Turned On in a Multi-Antenna Broadcast Channel
This paper considers broadcast channels with L antennas at the base station and m single-antenna users, where each user has perfect channel knowledge and the base station obtains c...
Wei Dai, Youjian Liu, Brian Rider
IANDC
2006
101views more  IANDC 2006»
15 years 6 months ago
Mind change efficient learning
This paper studies efficient learning with respect to mind changes. Our starting point is the idea that a learner that is efficient with respect to mind changes minimizes mind cha...
Wei Luo, Oliver Schulte