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ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
16 years 1 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
MICRO
2009
IEEE
144views Hardware» more  MICRO 2009»
16 years 1 months ago
Characterizing flash memory: anomalies, observations, and applications
Despite flash memory’s promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, ...
Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, ...
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
16 years 1 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee
BICOB
2009
Springer
16 years 1 months ago
Assembly of Large Genomes from Paired Short Reads
The de novo assembly of genomes from high-throughput short reads is an active area of research. Several promising methods have been recently developed, with applicability mainly re...
Benjamin G. Jackson, Patrick S. Schnable, Srinivas...
ATAL
2009
Springer
16 years 29 days ago
Context-aware multi-stage routing
In context-aware route planning, a set of agents has to plan routes on a common infrastructure and each agent has to plan a conflict-free route from a source to a destination wit...
Adriaan ter Mors, Jeroen van Belle, Cees Witteveen
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