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» On bounding the delay of a critical path
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DAC
2002
ACM
16 years 7 months ago
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ti...
GLOBECOM
2008
IEEE
16 years 15 days ago
A Dynamic Programming Approach for Routing in Wireless Mesh Networks
—The routing problem in Wireless Mesh Networks is concerned with finding “good” source-destination paths. It generally faces multiple objectives to be optimized, such as i) ...
Jorge Crichigno, Joud Khoury, Min-You Wu, Wei Shu
DAC
1995
ACM
15 years 9 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 10 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 11 months ago
High-speed VLSI architecture for parallel Reed-Solomon decoder
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
Hanho Lee