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» On bounding the delay of a critical path
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DATE
2003
IEEE
116views Hardware» more  DATE 2003»
15 years 11 months ago
Statistical Timing Analysis Using Bounds
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...
MICRO
2005
IEEE
123views Hardware» more  MICRO 2005»
15 years 11 months ago
A Criticality Analysis of Clustering in Superscalar Processors
Clustered machines partition hardware resources to circumvent the cycle time penalties incurred by large, monolithic structures. This partitioning introduces a long inter-cluster ...
Pierre Salverda, Craig B. Zilles
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
16 years 3 months ago
Interconnect-centric Array Architectures for Minimum SRAM Access Time
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...
ICC
2009
IEEE
145views Communications» more  ICC 2009»
15 years 3 months ago
End-to-End Delay Approximation in Cascades of Generalized Processor Sharing Schedulers
Abstract This paper proposes an analytical method to evaluate the delay violation probability of traffic flows with statistical Quality-of-Service (QoS) guarantees in a Generalize...
Paolo Giacomazzi, Gabriella Saddemi
ASPDAC
2006
ACM
153views Hardware» more  ASPDAC 2006»
16 years 22 hour ago
Diagonal routing in high performance microprocessor design
This paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan rout...
Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita,...