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DAC
2008
ACM
16 years 8 months ago
Automatic synthesis of clock gating logic with controlled netlist perturbation
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
Aaron P. Hurst
DAC
2004
ACM
16 years 7 months ago
Selective gate-length biasing for cost-effective runtime leakage control
With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power witho...
Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Denn...
DCC
2006
IEEE
16 years 6 months ago
Distortion Control for Queues with Deadlines
We investigate the optimum transmission strategy that minimizes the overall distortion for delaysensitive but distortion-tolerant data. We consider a set of source symbols residin...
Azadeh Faridi, Anthony Ephremides
AINA
2009
IEEE
16 years 1 months ago
Medium Access Control in Large Scale Clusters for Wireless Sensor Networks
—One of the main advantages of clustering algorithms is the ability to allow networks to be physically divided into smaller regions, thereby increasing the theoretical maximum nu...
Pedro N. E. S. Barbosa, Neil M. White, Nick R. Har...
INFOCOM
2009
IEEE
16 years 1 months ago
Effective Delay Control in Online Network Coding
—Motivated by streaming applications with stringent delay constraints, we consider the design of online network coding algorithms with timely delivery guarantees. Assuming that t...
João Barros, Rui A. Costa, Daniele Munarett...