Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit M...
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...