1529 search results - page 71 / 306 » On Timing Analysis of Combinational Circuits |
182
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LOPSTR
2004
Springer
15 years 11 months ago
2004
Springer
Offline partial evaluation techniques rely on an annotated version of the source program to control the specialisation process. These annotations guide the specialisation and have ...
164
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FPGA
1999
ACM
15 years 10 months ago
1999
ACM
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
164
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VTS
2003
IEEE
15 years 11 months ago
2003
IEEE
: This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation [1] is first p...
169
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ICCAD
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
161
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus pr...