2452 search results - page 248 / 491 » On Reduction of Lagrange Systems |
138
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ACSC
2005
IEEE
16 years 7 days ago
2005
IEEE
The Address Recalculation Pipeline is a hardware architecture designed to reduce the end-to-end latency suffered by immersive Head Mounted Display virtual reality systems. A deman...
188
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FPGA
2004
ACM
15 years 12 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
147
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LCTRTS
2004
Springer
15 years 12 months ago
2004
Springer
The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded ...
177
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QSIC
2003
IEEE
15 years 12 months ago
2003
IEEE
In this paper, we consider a problem that arises in black box testing: generating small test suites (i.e., sets of test cases) where the combinations that have to be covered are s...
181
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ISLPED
2003
ACM
15 years 12 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...