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» On Reduction of Lagrange Systems
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ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
16 years 3 months ago
Exploiting Microarchitectural Redundancy For Defect Tolerance
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
Premkishore Shivakumar, Stephen W. Keckler, Charle...
ICCAD
2003
IEEE
142views Hardware» more  ICCAD 2003»
16 years 3 months ago
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
The recent demand for system-on-chip RF mixed-signal design and aggressive supply-voltage reduction require chip-level accurate analysis of both the substrate and power delivery s...
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Ch...
CODES
2009
IEEE
16 years 1 months ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
ICASSP
2009
IEEE
16 years 1 months ago
Fast noise PSD estimation with low complexity
Although noise PSD estimation is a crucial part of noise reduction algorithms, most noise PSD estimators have problems in tracking non-stationary noise sources. Recently, a noise ...
Richard C. Hendriks, Richard Heusdens, Jesper Jens...
KBSE
2009
IEEE
16 years 1 months ago
Code Completion from Abbreviated Input
—Abbreviation Completion is a novel technique to improve the efficiency of code-writing by supporting code completion of multiple keywords based on non-predefined abbreviated inp...
Sangmok Han, David R. Wallace, Robert C. Miller