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DAC
2008
ACM
15 years 8 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
BMCBI
2010
243views more  BMCBI 2010»
15 years 6 months ago
Comparative study of unsupervised dimension reduction techniques for the visualization of microarray gene expression data
Background: Visualization of DNA microarray data in two or three dimensional spaces is an important exploratory analysis step in order to detect quality issues or to generate new ...
Christoph Bartenhagen, Hans-Ulrich Klein, Christia...
SIAMSC
2008
131views more  SIAMSC 2008»
15 years 6 months ago
Gramian-Based Model Reduction for Data-Sparse Systems
Model order reduction (MOR) is common in simulation, control and optimization of complex dynamical systems arising in modeling of physical processes and in the spatial discretizati...
Ulrike Baur, Peter Benner
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 3 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
EMSOFT
2005
Springer
16 years 2 days ago
A sink-n-hoist framework for leakage power reduction
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee