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GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
16 years 1 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
ICEIS
2008
IEEE
16 years 29 days ago
Internal Fraud Risk Reduction - Results of a Data Mining Case Study
Corporate fraud these days represents a huge cost to our economy. Academic literature already concentrated on how data mining techniques can be of value in the fight against frau...
Mieke Jans, Nadine Lybaert, Koen Vanhoof
ICPR
2008
IEEE
16 years 29 days ago
Parameter-based reduction of Gaussian mixture models with a variational-Bayes approach
This paper 1 proposes a technique for simplifying a given Gaussian mixture model, i.e. reformulating the density in a more parcimonious manner, if possible (less Gaussian componen...
Pierrick Bruneau, Marc Gelgon, Fabien Picarougne
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
16 years 26 days ago
Microarchitecture floorplanning for sub-threshold leakage reduction
Lateral heat conduction between modules affects the temperature profile of a floorplan, affecting the leakage power of individual blocks which increasingly is becoming a larger ...
Hushrav Mogal, Kia Bazargan
ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
16 years 24 days ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...