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DAC
2003
ACM
16 years 7 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
DAC
2005
ACM
16 years 7 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
DAC
2006
ACM
16 years 7 months ago
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, ...
ISBI
2008
IEEE
16 years 7 months ago
Deformation-based nonlinear dimension reduction: Applications to nuclear morphometry
We describe a new approach for elucidating the nonlinear degrees of freedom in a distribution of shapes depicted in digital images. By combining a deformation-based method for mea...
Gustavo K. Rohde, Wei Wang, Tao Peng, Robert F. Mu...
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
16 years 3 months ago
Reduction of Crosstalk Pessimism using Tendency Graph Approach
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred ...