Sciweavers

8728 search results - page 187 / 1746
» On Reduct Construction Algorithms
Sort
View
DAC
2004
ACM
16 years 7 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
ICML
2005
IEEE
16 years 7 months ago
Supervised dimensionality reduction using mixture models
Given a classification problem, our goal is to find a low-dimensional linear transformation of the feature vectors which retains information needed to predict the class labels. We...
Sajama, Alon Orlitsky
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
16 years 3 months ago
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
— Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis o...
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jia...
PIMRC
2008
IEEE
16 years 27 days ago
Optimal constellation distortion for PAR reduction in OFDM systems
Abstract—The high peak-to-average-power ratio (PAR) of Orthogonal Frequency Division Multiplexing (OFDM) transmission systems significantly reduces the power efficiency or perf...
Moshe Malkin, Brian S. Krongold, John M. Cioffi
ISQED
2005
IEEE
84views Hardware» more  ISQED 2005»
16 years 3 days ago
Performance Driven OPC for Mask Cost Reduction
With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an inte...
Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, J...