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ICML
2007
IEEE
16 years 7 months ago
Robust non-linear dimensionality reduction using successive 1-dimensional Laplacian Eigenmaps
Non-linear dimensionality reduction of noisy data is a challenging problem encountered in a variety of data analysis applications. Recent results in the literature show that spect...
Samuel Gerber, Tolga Tasdizen, Ross T. Whitaker
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 7 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
16 years 6 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
ICCAD
2006
IEEE
165views Hardware» more  ICCAD 2006»
16 years 3 months ago
A fast block structure preserving model order reduction for inverse inductance circuits
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
Hao Yu, Yiyu Shi, Lei He, David Smart
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
16 years 1 months ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson