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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 3 months ago
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
Tianpei Zhang, Sachin S. Sapatnekar
ITC
2002
IEEE
114views Hardware» more  ITC 2002»
15 years 11 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
LISP
2006
77views more  LISP 2006»
15 years 6 months ago
Expressing combinatory reduction systems derivations in the rewriting calculus
The last few years have seen the development of the rewriting calculus (also called rho-calculus or -calculus) that uniformly integrates first-order term rewriting and the -calculu...
Clara Bertolissi, Horatiu Cirstea, Claude Kirchner
IEEECIT
2010
IEEE
15 years 5 months ago
Superblock-Based Source Code Optimizations for WCET Reduction
—Superblocks represent regions in a program code that consist of multiple basic blocks. Compilers benefit from this structure since it enables optimization across block boundari...
Paul Lokuciejewski, Timon Kelter, Peter Marwedel
DAC
2008
ACM
16 years 7 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...